1. Field of the Invention
This invention relates to a process for designing a cleaning-apparatus line configuration in a manufacturing process for a semiconductor device, and a cleaning apparatus optimized for its line configuration according to the designing process.
2. Description of the Prior Art
In a process for manufacturing a semiconductor device, a variety of pretreatment and cleaning procedures are conducted before some steps such as forming a conductive material film and an insulating film on a semiconductor surface and a conductive material film on a dielectric material film. Such pretreatment/cleaning procedures include removing undesired or remaining materials from a previous step, e.g., an undesired photoresist mask, removing particles or residues inevitably remaining after a step such as dry etching; and exposing a clean surface used in the next step, e.g., removing an undesired oxide film formed on a surface of a semiconductor device or conductive material. Each pretreatment/cleaning has a specific purpose depending on steps before and/or after the procedure, and conducted with an appropriate means. When cleaning by selectively removing a film, particles or residues remaining in a small amount on a surface, a variety of etchants may be sometimes used to slightly etch the whole surface. Alternatively, a particular substance is selectively dissolved under mild conditions. Furthermore, two or more of these means may be combined to conduct a wet process meeting a requirement in each case.
A process for manufacturing a semiconductor device comprises several etching steps, some of which employ wet etching rather than dry etching in the light of suitability. These various wet etching steps themselves selectively dissolve and remove a target material layer or a given area, and at the end of etching, an etchant on a surface is thoroughly cleaned/removed.
In a wet process such as wet etching, cleaning and pretreatment, a whole substrate is immersed in an etchant for chemical treatment. An etchant employed in the wet process is usually used for removing adhering contaminants during another step or dissolving a film itself such as a resist or natural oxide film; i.e., for primarily dissolving and removing a substance of interest. However, a new material such as a special metal has been recently employed in a semiconductor device, so that as a special case, a substance not of interest may be concomitantly dissolved in an extremely small amount. Thus, besides ion species generated mainly after dissolving a substance of interest, there may be present ion species generated by a concomitant dissolution reaction in a very small amount in an etchant. For example, when dissolving and removing an oxide film on the rear face of a silicon substrate as a pretreatment, a very small amount of a conductive material layer formed on the surface of the silicon substrate is dissolved and thus ions derived from a metal element composing the conductive material (hereinafter, referred to as xe2x80x9cderived ionsxe2x80x9d) are generated in the etchant.
During washing an etchant adheringed to a surface with water after a wet process, a small amount of adhering etchant is diluted, so that the level of the above-mentioned various trace ion species is further lowered. As a result, it is quite rare that various molecules or ion species:dissolved in the etchant remain on the surface. The substrate surface, therefore, usually becomes considerably clean after the wet process. In other words, in each process, a process design and conditions are chosen to substantially eliminate element ions or compound molecules inevitably contained in an etchant from the surface by removing the etchant with water after the process.
There will be described a wet process in a manufacturing process for a MOSFET for a logic circuit whose manufacturing process has been already established. For a series of steps for manufacturing an N-MOSFET for a logic circuit, FIG. 6 shows the first half to the step of forming an FET while FIG. 7 shows the latter half from the step of forming an interlayer insulating film. Purposes of wet processes in the manufacturing process and types of dopants used therein will be described with reference to cross sections sequentially shown in FIGS. 6 and 7 according to the process order.
In the step illustrated in FIG. 6(a), on a silicon substrate 601 is formed a buried oxide film for separation between devices. On the substrate surface is formed a trench by a known etching technique. On the substrate surface on which the trench has been formed is deposited an oxide film 600 by a known bias CVD technique. Then, as illustrated in FIG. 6(a), the oxide film 600 is removed by a chemical-mechanical polishing (CMP) technique to expose the surface of the silicon substrate 601. The oxide film buried in the trench becomes a shallow trench isolation (STI) 602 (hereinafter, referred to as a xe2x80x9ctrench isolationxe2x80x9d) for separation between devices. In the above series of steps, the rear face of the wafer is cleaned after CMP for removing, e.g., an oxide film adhering to the rear face.
Subsequently, in the step illustrated in FIG. 6(b), for example, B (boron) as an N-type dopant is ion-implanted with given depth and doping amount according to a designed threshold voltage of an FET to form a doping area 603. After the step, the exposed silicon substrate 601 is covered with a natural oxide film formed during the step. The uneven natural oxide film is removed by dissolving and cleaning with an agent such, as diluted hydrofluoric acid (DHF; diluted HF). The exposed substrate surface is sequentially washed with an ammonium hydroxide-hydrogen peroxide mixture (APM), a hydrochloric acid-hydrogen peroxide mixture (HPM) or a sulfuric acid-hydrogen peroxide mixture (SPM), to remove contaminants adhering to the silicon substrate surface (the first cleaning step). Then, as illustrated in FIG. 6(b), on the clean surface thus obtained is formed a gate insulating film 604 with a given thickness.
Then, in the step illustrated in FIG. 6(b), on the gate insulating film 604 is deposited a polysilicon layer by CVD. Since the polysilicon layer is used as a gate, it is doped with, for example, an N-type dopant such as P (phosphorous) to a concentration of, e.g., about 1020 cmxe2x88x923 for endowing desired conductivity. Then, a resist pattern 630 to be an etching mask is formed by a known photolithography. Using the mask, the polysilicon is selectively etched by reactive dry etching using a reactive gas such as HBr and Cl2, to form a gate electrode shape. As shown in FIG. 6(c), the gate. insulating film 604 remains only under the gate electrode 605 while the insulating film 604 covering the other area is also removed.
The resist 630 is peeled off by SPM cleaning and then APM cleaning. The surface is cleaned with an ammonium hydroxide-hydrogen peroxide mixture (APM) and then HPM or SPM to remove contaminants and residual organic compounds on the polysilicon of the gate electrode 605 and the silicon surface in areas to be a source-drain area 606, 607 (the second cleaning step). Then, for example, P (phosphorous) as an N-type dopant is ion-implanted at a low level, using the gate electrode 605 as an implanting mask to form light-doping areas 606, 607.
Then, in the step illustrated in FIG. 6(d), an insulating film is deposited on the whole surface of the substrate including the polysilicon of the gate electrode 605. The insulating film is etched by dry etching with perpendicular anisotropy, so that only the insulating film deposited on the side wall of the gate electrode 605 can remain to form a side wall 605a. Then, for example, As (arsenic) as an N-type dopant is ion-implanted at a high level using the gate electrode 605 and the side wall 605a covering its wall as an implanting mask to form heavy-doping areas 608, 609. In this step, as shown in FIG. 6(d), there is formed a main part of a MOSFET with a self-aligned LDD structure.
Then, in the step illustrated in FIG. 6(e), on the top of the gate electrode 605, the source area 608 and the drain area 610 is formed the first conductive material layer 610 corresponding to the first interconnect (the lowest interconnect) in the interconnects connected to a transistor. Recently, a variety of metal silicides with good heat resistance have been applied as the first conductive material layer 610. For example, when using titanium silicide, titanium (Ti) is deposited on the whole surface of the polysilicon of the gate electrode 605, the side wall 605a covering its wall and one side of the substrate surface, and the product is heated at 690xc2x0 C. to silicide the area where the silicon surface is directly in contact with titanium. Then, unreacted titanium deposited on, for example, the side wall 605a, the trench separation 602 and the insulating film is selectively etched off. The product is subject to lamp annealing at 840xc2x0 C. to form a silicide layer as the first conductive material layer 610 closely adhering to the top of the gate electrode 605, the source area 608 and the drain area 609.
After the step in FIG. 6(e), a pad oxide film and a silicon oxide film may be formed on the whole surface of the substrate (not shown). In such a case, hydrofluoric-nitric acid(a mixture of hydrofluoric acid and nitric acid: HF+HNO3+H2O) is sprayed only on the rear surface of the substrate to remove a silicon nitride film adhering to the surface for cleaning the rear surface. Alternatively, after depositing a thicker silicon oxide film on the silicon nitride film in the substrate surface, the entire substrate is immersed in hot phosphoric acid to remove the silicon nitride film adhering to the rear surface of the substrate for cleaning the rear surface.
Then, in the latter step illustrated in FIG. 7, an interconnect to be connected with a transistor is formed. First, as shown in FIG. 7(f), on the substrate surface is deposited an insulating film as an interlayer insulating film 611 such as a silicon oxide film.
Then, in the step illustrated in FIG. 7(g), on the interlayer insulating film 611 is formed a resist pattern 612. Contact holes 613a, 613b penetrating the interlayer insulating film 611 is formed in given positions on the first conductive material layer 610 formed on the source area 608 and the drain area 609 by dry etching using the above resist pattern 612 as a mask. As shown in FIG. 7(g), the bottoms of the contact holes 613a, 613b reach the surface of the first conductive material 610. Similarly, in the gate electrode 605 is formed a contact hole reaching the surface of the first conductive material layer 610 formed on the polysilicon layer at a point not shown in this figure.
Before the step illustrated in FIG. 7(h), it is cleaned by SPM and APM cleaning for peeling/removing the resist pattern 612 (the third cleaning step). Subsequently, the surfaces of the first conductive material layer 610 such as a silicide layer exposed in the bottoms of the contact holes 613a, 613b are cleaned with, for example, APM, SPM or HPM, diluted hydrofluoric acid (DHF) or BHF, or FPM.
A conductive material is buried in the contact holes 613a, 613b for connecting the first conductive material layer 610 with an electrode interconnect formed on the interlayer insulating film 611 to form a plug 614. Specifically, on the exposed first conductive material layer 610 such as a silicide layer is selectively deposited, for example, polysilicon doped with phosphorous, an N-type dopant, as a conductive material for filling the contact holes as shown in FIG. (h) to form a plug 614. Similarly, a plug is formed in the contact hole formed on the gate electrode 605. As the above plugs, a layered structure of Ti, TiN and W may be used instead of polysilicon.
In the final step, electrode interconnects formed on the interlayer insulating film 611, i.e., a source and a drain electrode interconnects and a gate electrode interconnect, are formed such that they are connected to the corresponding plugs, respectively. Generally, in a MOSFET for a logic circuit, such a surface electrode interconnect is made of a metal such as aluminum and copper. When high-temperature resistance comparable to the first conductive material layer 610 is required, the surface electrode interconnect may be a metal silicide film such as tungsten silicide deposited by sputtering.
Next, a process for forming a memory cell area will be described with reference to FIG. 8. In a memory circuit such as a DRAM (dynamic random access memory), a capacitative element required in a memory device is formed in addition to a MOSFET. Specifically, the polysilicon gate 605 and the gate electrode interconnect 610g are used as a word line while the source 608 is connected to a bit line 615 formed on the interlayer insulating film 611 via the plug 614 and the source electrode 610s. A drain 609 is connected with a capacitative element 618 via a plug 621 and a drain electrode 610d. 
A MOSFET for a memory circuit is formed by the process as in the MOSFET for a logic circuit shown in FIGS. 6 and 7. However, a capacitative element connected to the drain 609 is instead formed in the process illustrated in FIG. 8, while only the contact hole 613b and the plug 614 are not formed on the drain 609 in the steps illustrated in FIGS. 7(g) and 7(h).
After the step illustrated in FIG. 7(h), on the interlayer insulating film 611 is formed a bit line 615 made of a metal silicide such that it is connected with the plug 614 on the source 608, as shown in FIG. 8(i).
In the step illustrated in FIG. 8(i), the interlayer insulating film 611 as well as the first interlayer film 616 covering the word line formed on the insulating film and the bid line 615 are first deposited. As shown in FIG. 8(i), a contact hole is formed, which penetrates the first interlayer film 616 and the interlayer insulating film 611 and reaches the surface of the first conductive material layer 610d formed on the drain 609.
Subsequently, before the step illustrated in FIG. 8(h), the surface of the first conductive material layer 610d (a silicide layer) exposed in the bottom of the contact hole is cleaned with, for example, APM, SPM or HPM, diluted hydrofluoric acid (DHF) or BHF, or FPM. On the exposed first conductive material layer 610d is selectively deposited, for example, polysilicon doped with phosphorous, an N-type dopant, as a conductive material for filling the contact hole 613b to form a contact plug 621.
On the first interlayer film 616 is formed the second interlayer film 617, and then a lower electrode 618, a dielectric film layer 619 and an upper electrode 620 are formed in sequence. The lower electrode 618 in a capacitative cell disposed on the first interlayer film 616 is formed to be tightly connected with the above contact plug 621 and electrically connected with the drain 609. As shown in FIG. 8(h), the upper electrode 620 is formed on the second interlayer film 617 while in the capacitative cell it is in contact with a dielectric film layer 619 such as a BST (BaxSr1-xTiO3), Ta2O5 or Si3N4 surface. Here, after depositing the dielectric film layer 619, its surface is cleaned and then the upper electrode is formed. When using a silicon nitride film as an insulating film of capacitor, a wafer is placed under a nitrogen atmosphere and heat-treated at an high temperature, e.g., about 890xc2x0 C. to nitride the surface of the lower electrode 618 to form a silicon nitride film. When using a tantalum oxide film as a capacitor insulating film, a wafer is annealed at an elevated temperature of 750 to 850xc2x0 C. (high temperature baking) for phase transition in a crystal structure to form the dielectric film layer 619 with a desired dielectric constant.
As described above, when tight contact is required between different materials, pretreatment/cleaning is conducted with a variety of etchants for providing a clean surface before, for example, depositing a conductive material on a silicon substrate surface, depositing polysilicon on a silicide film, depositing a conductive material on a polysilicon surface, or forming a gate insulating film on a silicon substrate surface. Etchants which may be used in a wet process include, an ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM) and diluted hydrofluoric acid (DHF) as described above, as well as an ammonium fluoride buffer-hydrofluoric acid mixture(BHF: buffered HF), 50% hydrofluoric acid(HF), a hydrochloric acid-hydrogen peroxide mixture (HPM), phosphoric acid and hydrofluoric-nitric acid (a hydrofluoric acid-nitric acid mixture).
In commercial production, a plurality of silicon substrates in the same lot are simultaneously subject to a sequential process according to a series of production steps for mass production. Alternatively, a plurality of silicon substrates belonging to different product lots are simultaneously subject to a sequential process. In the process, it is often that while treating the plurality of substrates composing the above group, etchants used in individual wet processes are continuously used without being replaced. Cleaning performance of an etchant used in a wet process treatment is gradually changed, i.e., gradual reduction in cleaning performance so that it is necessary to replace with a new etchant. Until replacement, the plurality of silicon substrates passing through the same steps are sequentially processed. As the total number of treated substrates increases, for example, various element ion species dissolved during the wet process treatment are accumulated. As described above, each wet process is designed and chosen to prevent the above various element ion species dissolved during the wet process treatment from remaining on a surface after washing an etchant even when the various element ion species are accumulated in the etchant.
Various types of etchant have been studied for a wet process, and the same type of etchant is used in some wet processes. If various element ion species dissolved in an etchant are common and do not remain on or contaminate a surface in a plurality of wet processes employing the same type of etchant, the plurality of wet process may share the same etchant. In an established production process, an etchant is shared in an attempt to reduce the total number of etchant vessels used in a wet process. Such etchant sharing has been applied to a commercial production process after demonstrating that it does not affect properties or reliability of a semiconductor device produced.
It is ideal to optimize a cleaning-apparatus line configuration used in a series of wet processes, particularly to reduce the total number of etchant vessels by etchant sharing, after such a demonstration test. A demonstration test, however, often takes much time. For example, when replacing a particular material composing a semiconductor device with another material because of change of design, a wet process in which an etchant can be shared without causing contamination derived from the newly employed material should be selected. Here, it will take a considerably longer time for application to a commercial production process, if suitability of the selection is determined based on demonstration test results including its effects on reliability in device properties. Furthermore, while the laboratory level of demonstration test, an additional demonstration test simulating a mass production line is required in a trial production line, which takes more time.
Therefore, when there is not enough time to fully conduct the above demonstration test, an etchant to be in contact with a newly employed material is separated from etchants used in the other wet processes to avoid etchant sharing. By avoiding etchant sharing as described above, possibility of cross contamination derived from a newly employed material has been physically eliminated to temporarily conduct commercial mass production. In other words, it has been a practice to use a cleaning apparatus or wet processing apparatus exclusively for an etchant to be in contact with a newly employed material for avoiding cross contamination. It has often lead to unnecessary increase in the number of apparatuses, an unnecessary apparatus cost, increase in an etchant cost, increase of an occupied area for placing an apparatus, and even increase in a cost for treating a used etchant and increase of the amount of industrial wastes subject to final disposal.
Thus, it has been desired to suggest a process for designing a cleaning-apparatus line configuration in a process for manufacturing a silicon semiconductor device, which facilitates etchant sharing while eliminating cross contamination derived from a newly employed material after a short-time investigation, for minimizing increase the above unnecessary cost increases and increase in the amount of dopants requiring final disposal as much as possible.
An objective of this invention resolving the above problems is to provide a process for selecting in a short time a wet process treatment in which an etchant can be shared based on a minimum preliminary, investigation and which does not require a long-time demonstration test for investigating etchant sharing while eliminating cross contamination derived from a newly employed material, i.e., a process for designing a cleaning-apparatus line configuration in a process for manufacturing a semiconductor device, which appropriately facilitates etchant sharing. More specifically, an objective of this invention is to provide a process for selecting a wet process or cleaning treatment in which an etchant can be shared based on simple selection criteria and procedures and which utilizes only a few of preliminary investigation results while substantially eliminating cross contamination derived from a newly employed material, when employing the new material because of change of design on the basis of a series of wet processes and a cleaning-apparatus line configuration constituting an established manufacturing process in which an etchant is optimally shared. Another objective of this invention is to provide a process for selecting a wet process or cleaning treatment according to convenient selection criteria or procedures, in which an etchant can be shared, substantially eliminating cross contamination by adding an additive substantially without changing an etchant composition when cross contamination derived from a new material is concerned in a previously employed etchant as a result of selection of a wet process or cleaning treatment in which an etchant can be shared, on the basis of a few of preliminary investigation results described above.
Further objective of this invention is to provide a cleaning apparatus which is designed by applying the above process for designing a cleaning-apparatus line configuration in a process for manufacturing a semiconductor device and which can conduct required various cleaning procedures without significant reduction in a cleaning effect in a smaller number of apparatuses. Further objective of this invention is to provide a process for manufacturing a semiconductor device, using a more effective wet process configuration, which employs an optimized cleaning apparatus and cleaning procedure designed by applying the above process for designing a cleaning-apparatus line configuration in a process for manufacturing a semiconductor device.
This invention provides a process for designing a cleaning-apparatus line configuration used in a wet process in a process for manufacturing a semiconductor device, comprising the steps of:
estimating a presumed concentration of dissolved contaminant elements accumulated in the same etchant used in a plurality of wet processes;
estimating a residual amount of the contaminant elements adhering to a substrate from the estimated concentration of dissolved contaminants;
evaluating sharing of the etchant in the plurality of wet processes when the estimated residual amount of the contaminant elements is less than a given reference value which is the highest value where device properties are not affected; and
conducting sharing of the etchant in a cleaning-apparatus line configuration used in a wet process on the basis of the decision.
More specifically, this invention provides a process for designing a cleaning-apparatus line configuration used in a wet process in a process for manufacturing a semiconductor device, wherein on the basis of results obtained by conducting, for various materials constituting the semiconductor device, the following preliminary tests:
(a) a dissolution test for determining whether the materials are dissolved in an etchant for all etchants used in two or more wet processes in the manufacturing process;
(b) a dissolution rate test assessing the etchant dissolving the material for the amount of the dissolved material per a unit area of the material and a unit time;
(c) an adhesion property test comprising the steps of dissolving ion or molecule species generated when dissolving the material, to a given high concentration in the etchant; immersing a clean substrate in the high concentration solution for a given time; then removing the etchant by washing with a usual procedure; and determining presence of adhering residual elements derived from the material on the substrate surface;
(d) an adhesion-property concentration dependency test where for an element derived from the material which has been determined to remain by adhesion in the adhesion property test, a correlation is determined between the concentration of the dissolved element in the etchant and its surface density adhering to the substrate surface;
(e) an effective adhesion-inhibitor selection test comprising the step of determining a re-adhesion inhibiting agent which after being added to the etchant, forms a complex or compound with the ion or molecular species of the element derived from the material which has been determined to remain by adhesion in the adhesion property test, to reduce the adhesional residue,
sharing an etchant used in a wet process where the etchant is inevitably in contact with the material between the process and another wet process is evaluated in a manner that considering the following selection criteria:
(i) an etchant which is determined not to dissolve the material in the dissolution test in (a);
(ii) an etchant which is determined that there are no residues by adhesion in the adhesion property test in (c);
(iii) an etchant which has been determined that there are residues by adhesion in the adhesion property test in (c) and which is determined that an estimated adhesion surface density is less than a given contaminant surface density limit within which the properties of the semiconductor device are not deteriorated, by calculating an estimated concentration of dissolved ion or molecular species of an element derived from the material accumulated by dissolution in the etchant when processing a given number of substrates according to the structure of the semiconductor device, based on the dissolution rate obtained in the dissolution rate test in (b) and determining the estimated adhesion surface density from the estimated dissolution concentration, based on the correlation between the dissolution concentration in the etchant determined in the adhesion-property concentration dependency test in (d) and the surface density of the residues adhering to the silicon substrate surface;
(iv) an etchant containing a re-adhesion inhibitor, which is evaluated that in the selection criterion in (iii) the estimated adhesion surface density is equal to or higher than the contaminant surface density limit and is evaluated in a re-estimation that an estimated adhesion surface density becomes lower than the contaminant surface density limit by adding the re-adhesion inhibitor which is determined to be effective in the effective adhesion-inhibitor selection test in (e),
an etchant meeting the selection criteria (i) to (iii) can be shared; an etchant further meeting the selection criterion (iv) can be shared after adding the re-adhesion inhibitor determined to be effective, or otherwise an remaining etchant can be shared only in wet processes where the etchant is not inevitably in contact with a material which may be a source of an element suspected to cause deterioration of the properties of the semiconductor device, and
according to the evaluation, etchant sharing is employed in a cleaning-apparatus line configuration used in a wet process.
For example, the upper limit in a distribution range of a surface density of an element derived from the material, which is present on a substrate by immersing a clean substrate in an etchant free from the ion or molecule species of an element derived from the material for a given period and removing the etchant by a usual washing procedure, may be chosen the given contaminant surface density limit, which does not cause deterioration of the properties of the semiconductor device. Such selection of the contaminant surface density limit is usually preferable because it may reliably eliminate cross contamination.
Particularly, the process for designing a cleaning-apparatus line configuration of this invention is useful when the various materials constituting the semiconductor device include a material which may cause property deterioration when an element derived from the material adheres to a substrate surface before the step handling the material. For example, the designing process is particularly preferable when the various materials include cobalt or cobalt silicide.
Furthermore, the designing process of this invention is more suitable when the etchant employed in two or more wet processes in the process for manufacturing a semiconductor device is an ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), diluted hydrofluoric acid,(DHF), an ammonium fluoride buffer-hydrofluoric acid mixture(BHF: buffered HF), a hydrofluoric acid-hydrogen peroxide mixture (FPM), 50% hydrofluoric acid(HF), a hydrochloric acid-hydrogen peroxide mixture (HPM), phosphoric acid and/or hydrofluoric-nitric acid (a hydrofluoric acid-nitric acid mixture).
This invention also provides, a process for designing a cleaning-apparatus line configuration where a wafer on which a semiconductor device is formed is cleaned with an etchant in a process for manufacturing a semiconductor device, wherein the manufacturing process comprises a step of cleaning the wafer on which a material used in the semiconductor device is exposed, with a given etchant, and comprising the steps of:
estimating a dissolution concentration of the material exposed on the wafer surface in the etchant;
determining a surface density of the material adhering to the wafer when immersing the wafer in the etchant in which the material is dissolved at the estimated dissolution concentration for a given period;
evaluating that the etchant can be shared in another cleaning step when the adhesion surface density is lower than a given contaminant surface density limit defined according to whether the adhesion surface density affects the properties of the semiconductor device;
evaluating that the etchant cannot be shared in another cleaning step when the adhesion surface density is higher than a given contaminant surface density limit; and
designing a cleaning-apparatus line configuration according to the evaluation results.
In the designing process, the step of estimating the dissolution concentration may comprise estimating a concentration corresponding to an accumulated concentration by dissolution of ion or molecule species of an element derived from the material when cleaning a given number of wafers on which the material is exposed for a given period.
Alternatively, the step of estimating the dissolution concentration may comprise the steps of:
estimating an amount of the material dissolved in the etchant per a unit area and a unit time as a dissolution rate test; and
estimating the dissolution concentration by multiplying the dissolution rate obtained in the dissolution rate test by the sum of the area where the material is exposed on the surface of the mass-production wafer used for a given mass production and by the sum of the time for cleaning the mass-production wafer until the etchant is replaced.
In the step of estimating dissolution concentration, the wafer on which the material is exposed may be a mass-production wafer used in mass production, or a wafer in which the material is surface-processed as in the mass-production wafer and on which the material is exposed in an area equal to or larger than that in the mass-production wafer.
Furthermore, in the step of determining the adhesion surface density, the adhesion surface density may be determined after adding a re-adhesion inhibitor which forms a complex with ion or molecule species of an element derived from the material. Alternatively, in the step of determining an adhesion density, the adhesion surface density may be determined by
when ion or molecule species of an element derived from the material are dissolved in the etchant at various given concentrations, determining a surface density of the material adhering to the wafer after immersing the wafer in the etchant at each the given concentration for a given period to determine a correlation between the given concentration and the adhesion surface density on the wafer; and
determining a surface density of the material adhering to the wafer after immersing the wafer in the etchant at a given concentration for a given period on the basis of the correlation.
This invention also provides a cleaning-apparatus line configuration designed according to any of the above designing processes.
The cleaning-apparatus line configuration of this invention is characterized in that an etchant is shared according to the above designing process. More specifically, this invention provides a cleaning-apparatus line configuration used in a wet process in a process for manufacturing a semiconductor device, wherein on the basis of results obtained by conducting, for various materials constituting the semiconductor device which are subject to wet processes in the cleaning-apparatus, the following preliminary tests:
(a) a dissolution test for determining whether the materials are dissolved in an etchant used in two or more wet processes in the manufacturing process;
(b) a dissolution rate test assessing the etchant dissolving the material for the amount of the dissolved material per a unit area of the material and a unit time;
(c) an adhesion property test comprising the steps of dissolving ion or molecule species generated when dissolving the material, to a given high concentration in the etchant; immersing a clean substrate in the high concentration solution for a given time; then removing the etchant by washing with a usual procedure; and determining presence of adhering residual elements derived from the material on the substrate surface;
(d) an adhesion-property concentration dependency test where for an element derived from the material which has been determined to remain by adhesion in the adhesion property test, a correlation is determined between the concentration of the dissolved element in the etchant and its surface density adhering to the substrate surface;
(e) an effective adhesion-inhibitor selection test comprising the step of determining a re-adhesion inhibiting agent which after being added to the etchant, forms a complex or compound with the ion or molecular species of the element derived from the material which has been determined to remain by adhesion in the adhesion property test, to reduce the adhesional residue,
sharing an etchant used in a wet process where the etchant is inevitably in contact with the material between the process and another wet process is evaluated in a manner that classifying the etchant according to the selection criteria consisting of the following (i) to (iv):
(i) an etchant which is determined not to dissolve the material in the dissolution test in (a);
(ii) an etchant which is determined that there are no residues by adhesion in the adhesion property test in (c);
(iii) an etchant which has been determined that there are residues by adhesion in the adhesion property test in (c) and which is determined that an estimated adhesion surface density is less than a given contaminant surface density limit within which the properties of the semiconductor device are not deteriorated, by calculating an estimated concentration of dissolved ion or molecular species of an element derived from the material accumulated by dissolution in the etchant when processing a given number of substrates according to the structure of the semiconductor device, based on a dissolution rate obtained in the dissolution rate test in (b) and determining the estimated adhesion surface density from the estimated dissolution concentration, based on the correlation between the dissolution concentration in the etchant determined in the adhesion-property concentration dependency test in (d) and the surface density of the residues adhering to the silicon substrate surface;
(iv) an etchant containing a re-adhesion inhibitor, which is determined that in the selection criterion in (iii) the estimated adhesion surface density is equal to or higher than the contaminant surface density limit and is determined in a re-estimation that an estimated adhesion surface density is lower than the contaminant surface density limit by adding the re-adhesion inhibitor which is determined to be effective in the effective adhesion-inhibitor selection test in (e), and
an etchant is shared in a cleaning-apparatus line configuration used in a wet process such that an etchant meeting the selection criteria (i) to (iii) can be shared; an etchant further meeting the selection criterion (iv) can be shared after adding the re-adhesion inhibitor determined to be effective, or otherwise an remaining etchant can be shared only in wet processes where the etchant is not inevitably in contact with a material which may be a source of an element suspected to cause deterioration of the properties of the semiconductor device.
For example, may be the upper limit in a distribution range of a surface density of an element derived from the material, which is present on a substrate by immersing a clean substrate in an etchant free from the ion or molecule species of an element derived from the material for a given period and removing the etchant by a usual washing procedure, may be chosen a given contaminant surface density limit, which does not cause deterioration of the properties of the semiconductor device. Such selection of the contaminant surface density limit is preferable because it may reliably eliminate cross contamination and usually used in manufacturing a wider range of semiconductor devices.
Particularly, the cleaning-apparatus line configuration of this invention is useful when the various materials constituting the semiconductor device include a material which may cause property deterioration when an element derived from the material adheres to a substrate surface before the step handling the material. For example, the line configuration is particularly preferable when the various materials include cobalt or cobalt silicide.
Furthermore, the line configuration of this invention is more suitable when the etchant employed in two or more wet processes in the process for manufacturing a semiconductor device where processing is conducted in the cleaning-apparatus line configuration is only an ammonium hydroxide-hydrogen peroxide mixture (APM), a sulfuric acid-hydrogen peroxide mixture (SPM), diluted hydrofluoric acid (DHF), an ammonium fluoride buffer-hydrofluoric acid mixture(BHF: buffered HF), a hydrofluoric acid-hydrogen peroxide mixture (FPM), 50% hydrofluoric acid(HF) and/or a hydrochloric acid-hydrogen peroxide mixture (HPM).